1. Field of the Invention
Example embodiments of the present invention in general are related to a half-duplex low-voltage differential signaling half-duplex transceiver of the system, and a pre-driver of the transceiver.
2. Description of the Related Art
Normally, half-duplex communication systems enable data communication between circuit module chips on printed circuit boards. A half-duplex communication system is typically composed of one or more half-duplex transceivers embedded in each of the circuit module chips. The half-duplex transceivers perform alternating operations of transmitting signals toward the opposite sites and receiving signals from the opposite sites. To perform these operations, each half-duplex transceiver includes a transmitter and a receiver.
As such, the transmitter and receiver in a half-duplex transceiver must be able to process high frequency data signals. In order to accomplish high-frequency data communication, the transmitter and receiver of the half-duplex transceiver are operable with high-frequency data signals. Although configuring a receiver to handle high-frequency data signals is rather straight forward, it is difficult even now to configure a transmitter for transferring data signals at high frequency because of limitations related to the power application needed for transmitting the data signals.
Conventional half-duplex transmitters employed in half-duplex communication systems for high-frequency data communication include current-mode transceivers, low-voltage differential signaling transceivers and duplex low-voltage differential signaling transceivers. However, these conventional transceivers are generally not robust for conducting high-frequency data communication. This is explained with reference to FIGS. 1 through 3, which illustrate half-duplex communication systems, each figure respectively illustrating a current-mode transceiver, a low-voltage differential signaling transceiver and a duplex low-voltage differential signaling transceiver.
FIG. 1 is a circuit diagram of a conventional half-duplex communication system employing a current-mode transceiver. In FIG. 1, output drivers 10 and 12 in a half-duplex communication system configured for a current mode to differentially amplify non-inverse and inverse data signals on non-inverse and inverse input lines (FDP and FDN, or SDP and SDN), to be transferred through non-inverse and inverse transceiver line TLN toward a corresponding input driver 20 and 22 on another circuit module chip.
In operation, an output driver 10 or 12 controls the amount of current flowing into a current sink CRS11 through a sink node SN11. This is done using a first NMOS transistor MN11 in the non-inverse transmission line TLP responding to the non-inverse input line FDP (or SDP), and by way of controlling the current flowing into the current sink CRS11 through the sink node SN11 using a second NMOS transistor MN12 in the inverse transmission line TLN responding to the inverse input line FDN (or SDN). Thus, non-inverse and inverse data signals transferred respectively through the non-inverse and inverse transmission lines TLP and TLN have waveforms which are configured such as to asymmetrically oscillate on the center level between a high potential VDD and a low potential VSS.
In addition, the half-duplex communication system of FIG. 1 prevents reflection of signals by connecting terminal resistors RL11 through RL14, having a resistance of 50Ω. These resistors are provided at both ends of the non-inverse and inverse transmission lines TLP and TLN. By connecting the terminal resistors RL11 through RL14 to the non-inverse and inverse transmission lines TLP and TLN in parallel, the non-inverse and inverse data signals transferred through the corresponding non-inverse and inverse transmission lines TLP and TLN oscillate at a 20 mV amplitude, as currents of about 8 mA flow through the non-inverse and inverse transmission lines TLP and TLN. As a result, the current-mode half-duplex communication system is a heavy consumer of current.
In an effort to address the problems in the current-mode half-duplex communication system of FIG. 1, another conventional half-duplex communication system has been proposed for processing low-voltage differential signals, as shown in FIG. 2. In a conventional half-duplex communication system for low-voltage differential signals, an output driver 30 (or 32) includes first PMOS transistor MP31 and second PMOS transistor MP32. PMOS transistors MP31 and MP32 regulate the amount of current flowing to the non-inverse transmission line TLP and the inverse transmission line TLN coming from a first sink node SN31 connected to a first current sink CRS31. The first and second NMOS transistors MN31 and MN32 also regulate the amount of current flowing from the non-inverse and inverse transmission lines TLP and TLN to a second sink node SN32 that is connected to a second current sink CRS32.
Accordingly, non-inverse and inverse data signals on corresponding non-inverse and inverse input lines FDP and FDN (or SDP and SDN) are amplified in differential modes. Therefore, in the conventional low-voltage differential signaling half-duplex communication system of FIG. 2, the non-inverse and inverse data signals that symmetrically oscillate on the center level between the high and low potentials are transferred through the non-inverse and inverse transmission lines TLP, TLN.
Further in the conventional low-voltage differential signaling half-duplex communication system of FIG. 2, a single terminal resistor RL21 (or RL22) is connected between the non-inverse and inverse transmission lines TLP and TLN that connect the output driver 30 (or 32) with an input driver 20 (or 22). Thus, in the conventional low-voltage differential signaling half-duplex communication system of FIG. 2, as the PMOS transistor MP31 and MP32 and the NMOS transistors MN31 and MN32 are turned on or off, it is difficult for a pre-driver (not shown, which supplies differential data signals to the output driver 30 or 32) to operate at a high frequency. Due to this difficulty, conventional low-voltage differential signaling half-duplex communication system is regarded as inadequate in an environment where data signals are transferred among circuit module chips at high frequencies.
In an effort to overcome the limitations in transferring high frequency data signals in conventional low-voltage differential signaling half-duplex communication systems, a conventional half-duplex communication system for low-voltage differential signals has been proposed, as shown in FIG. 3. Referring to FIG. 3, an output driver 50 (or 52) which is configured different than the output driver 30 (or 32 of FIG. 2), includes PMOS transistors MP51 and MP52 and NMOS transistors MN51 and MN52 in order to respond to respective duplex differential data signals, i.e., non-inverse and inverse P-channel data signals, and non-inverse and inverse N-channel data signals. To preliminarily amplify these duplex differential data signals, a pre-driver 40 (or 42) is used. The pre-driver 40 or 42 includes a P-channel amplifier (composed of three PMOS transistors MP31˜MP33), and an N-channel amplifier (composed of three NMOS transistors MN31˜MN33). With the pre-driver 40 or 42 in this configuration, it is possible for the low-voltage differential signaling half-duplex communication system to transfer high-frequency data signals.
However, in the conventional low-voltage differential signaling half-duplex communication system of FIG. 3, since the pre-driver 40 (or 42) activates the P-channel and N-channel differential data signals using independent circuits without synchronization, a skew occurs between the duplex differential data signals. As a result, the conventional system of FIG. 3 operates inefficiently in the application of high-frequency communication between circuit module chips on a printed circuit board. Additionally, the use of these independent circuits complicates the pre-driver 40 (or 42) configuration (i.e., requires twice as many components). Moreover, the system of FIG. 3 requires a complex duplex differential data signal source (i.e., a parallel-to-serial data converter that is called a “data multiplexer” in a semiconductor memory chip) for supplying the duplex differential data signals to the pre-driver 40 (or 42).